The present invention relates to an automatic compensation circuit for use with an analog multiplier. As is known in the prior art, analog multipliers are utilized for a wide variety of applications. For instance, in an electrical power measurement application where accurate power consumption measurement is desired, a first signal representing instantaneous voltage potential is multiplied with a second signal representing instantaneous electrical current with the resulting third product signal representing power consumption in wattage (V.times.Icos.theta.=W).
Analog multipliers used in such environment can therefore be utilized in an electronic watt-hour meter in order to provide the necessary calculation for determining watt-hour consumption. It is quite important that the power consumption be extremely accurate over a wide range of current input values. However, a problem with using an analog multiplier to perform the calculation is that current and voltage offsets occur because of transistor mismatches within the analog multiplier which can introduce errors into the power measurement calculation.
In particular, proportionally large error signals can be introduced into the power calculation during periods when the current signals are small. Because of the inherent limitations with analog multipliers, the calculation will likely have some value other than the true expected value, which is clearly undesirable. One prior art approach utilizes potentiometers which are set up during production testing to provide zero output offset, which requires extra time and component costs. This requirement for stabilizing the offset characteristics of an analog multiplier is an undesirable problem which has been generally present in such implementations.
While automatic compensation techniques are generally known, there have not been any such applications for use with an analog multiplier, which would reduce the component cost and provide improved accuracy. It would be desirable, therefore, to overcome these deficiencies by providing an improved implementation which eliminates the prior art approaches. In view of the above background, it is an objective of the present invention to provide an automatic compensation circuit for use with an analog multiplier.